Not Supported

[Peter]

Deleted.

[Charles Pegge]

Hi Peter,

It seems to be ok. I think the problem is the edx register gets overwritten when mul or imul is used.

the edx register receives the upper dword following a dword multiplication.

Charles

[Charles Pegge]

Hi Peter,

The Pentium supports two forms of imul with different opcodes: the newer form takes 2 operands, and a number:

69 /r id IMUL r32, r/m32,imm

mov eax,3
imul eax,eax,10000
print eax

Charles

[Charles Pegge]

I looked up imul to make sure O2 assembler was compliant: Only the 1-operand format alters the edx register.

Description
Performs a signed multiplication of two operands. This instruction has three forms,
depending on the number of operands.
• One-operand form — This form is identical to that used by the MUL instruction.
Here, the source operand (in a general-purpose register or memory location) is
multiplied by the value in the AL, AX, EAX, or RAX register (depending on the
operand size) and the product is stored in the AX, DX:AX, EDX:EAX, or RDX:RAX
registers, respectively.
• Two-operand form — With this form the destination operand (the first
operand) is multiplied by the source operand (second operand). The destination
operand is a general-purpose register and the source operand is an immediate
value, a general-purpose register, or a memory location. The product is then
stored in the destination operand location.
• Three-operand form — This form requires a destination operand (the first
operand) and two source operands (the second and the third operands). Here,
the first source operand (which can be a general-purpose register or a memory
location) is multiplied by the second source operand (an immediate value). The
product is then stored in the destination operand (a general-purpose register).
When an immediate value is used as an operand, it is sign-extended to the length of
the destination operand format.
The CF and OF flags are set when significant bit (including the sign bit) are carried
into the upper half of the result. The CF and OF flags are cleared when the result
(including the sign bit) fits exactly in the lower half of the result.
The three forms of the IMUL instruction are similar in that the length of the product
is calculated to twice the length of the operands. With the one-operand form, the
product is stored exactly in the destination. With the two- and three- operand forms,
however, the result is truncated to the length of the destination before it is stored in
the destination register. Because of this truncation, the CF or OF flag should be tested
to ensure that no significant bits are lost.
The two- and three-operand forms may also be used with unsigned operands
because the lower half of the product is the same regardless if the operands are
Opcode Instruction 64-Bit
Mode
Compat/
Leg Mode
Description
69 /r id IMUL r32, imm32 Valid Valid doubleword register ← r/m32 ∗
immediate doubleword.
REX.W + 69 /r id IMUL r64, imm32 Valid N.E. Quadword register ← r/m64 ∗
immediate doubleword.
NOTES:
* In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is
used: AH, BH, CH, DH.signed or unsigned.
Vol. 2A 3-497
INSTRUCTION SET REFERENCE, A-M
IMUL—Signed Multiply

Intel® 64 and IA-32 Architectures
Software Developer’s Manual
Volume 2A:

Charles

[Charles Pegge]

Ok Peter, Internally it is a three operand encoding, but the first two can be expressed as one, if they are the same register. I could support that in the next release, If you like.

This is how it goes in binary:

imul ecx,ecx,42  -------> imul ecx,42
opcode:
imul imm8         ecx  ecx   42
0110-1011   11-001-001  00101010

imul ecx,edx,42
opcode
imul imm8         edx  ecx   42
0110-1011   11-010-001  00101010


Charles

[Charles Pegge]

I have patched it in, ready for the next release.